CD4049UBE Integrated Circuit Chip CMOS HEX BUFFERS / CONVERTERS

CD4049UB, CD4050B

CMOS Hex Buffer/Converters

The CD4049UB and CD4050B devices are inverting and non-inverting hex buffers, respectively, and feature logiclevel conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL/TTL converters and can drive directly two DTL/TTL loads. (VCC = 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.)

The CD4049UB and CD4050B are designated as replacements for CD4009UB and CD4010B, respectively. Because the CD4049UB and CD4050B require only one power supply, they are preferred over the CD4009UB and CD4010B and should be used in place of the CD4009UB and CD4010B in all inverter, current driver, or logic-level conversion applications. In these applications the CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be substituted for these devices in existing as well as in new designs. Terminal No. 16 is not connected internally on the CD4049UB or CD4050B, therefore, connection to this terminal is of no consequence to circuit operation. For applications not requiring high sink-current or voltage conversion, the CD4069UB Hex Inverter is recommended.

Features

• CD4049UB Inverting

• CD4050B Non-Inverting

• High Sink Current for Driving 2 TTL Loads

• High-To-Low Level Logic Conversion

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and 25℃

• 5V, 10V and 15V Parametric Ratings

Applications

• CMOS to DTL/TTL Hex Converter

• CMOS Current “Sink” or “Source” Driver

• CMOS High-To-Low Logic Level Converter

Pinouts

Functional Block Diagrams

Schematic Diagrams

Absolute Maximum Ratings

Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55℃ to 125℃

Thermal Information

Package Thermal Impedance, θ_JA (see Note1):

    E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67℃/W

    D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73℃/W

    DW (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57℃/W

    NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64℃/W

    PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 108℃/W

Maximum Junction Temperature (Plastic Package) . . . . . . . . .150℃

Maximum Storage Temperature Range. . . . . . . . . . . 65℃ to 150℃

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265℃

    SOIC - Lead Tips Only

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7.

Stock Offer (Hot Sell)