HIP6501ACBZ-T Electronic IC Chips Triple Linear Power Controller

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HIP6501A

Triple Linear Power Controller with ACPI Control Interface

The HIP6501A, paired with either the HIP6020 or HIP6021, simplifies the implementation of ACPI-compliant designs in microprocessor and computer applications. The IC integrates two linear controllers and a low-current pass transistor, as well as the monitoring and control functions into a 16-pin SOIC package.

One linear controller generates the 3.3V_DUAL voltage plane from an ATX power supply’s 5VSB output during sleep states (S3, S4/S5), powering the PCI slots through an external pass transistor, as instructed by the status of the 3.3V_DUAL enable pin. An additional pass transistor is used to switch in the ATX 3.3V output for PCI operation during S0 and S1 (active) operatingstates.

The second linear controller supplies the computer system’s 2.5V/3.3V memory power through an external pass transistor in active states. During S3 state, an integrated pass transistor supplies the 2.5V/3.3V sleep-state power. A third controller powers up a 5VDUAL plane by switching in the ATX 5V output in active states, or the ATX 5VSB in sleep states.

The HIP6501A’s operating mode (active-state outputs or sleep-state outputs) is selectable through two control pins: S3 and S5. Further control of the logic governing activation of different power modes is offered through two enabling pins: EN3VDL and EN5VDL. In active states, the 3.3V_DUAL linear regulator uses an external N-Channel pass MOSFET to connect the output (V_OUT1) directly to the 3.3V input supplied by an ATX (or equivalent) power supply, while incurring minimal losses.

In sleep state, the 3.3V_DUAL output is supplied from the ATX 5VSB through an NPN transistor, also external to the controller. Active state power delivery for the 2.5/3.3V_MEM output is done through an external NPN transistor, or an NMOS switch for the 3.3V setting. In sleep states, conduction on this output is transferred to an internal pass transistor. The 5V_DUAL output is powered through two external MOS transistors.

In sleep states, a PMOS (or PNP) transistor conducts the current from the ATX 5VSB output, while in active states, current flow is transferred to an NMOS transistor connected to the ATX 5V output. Similar to the 3.3V_DUAL output, the operation of the 5V_DUAL output is dictated not only by the status of the S3 and S5 pins, but that of the EN5VDL pin as well.

Features

• Provides 3 ACPI-Controlled Voltages

  - 5V Active/Sleep (5V_DUAL)

  - 3.3V Active/Sleep (3.3V_DUAL)

  - 2.5V/3.3V Active/Sleep (2.5V_MEM)

• Simple Control Design

  - No Compensation Required

• Excellent Output Voltage Regulation

  - 3.3VDUAL Output: ±2.0% Over Temperature; Sleep States Only

  - 2.5V/3.3V Output: ±2.0% Over Temperature; Both Operational States (3.3V setting in sleep only)

• Fixed Output Voltages Require No Precision External Resistors

• Small Size

  - Small External Component Count

• Selectable 2.5VMEM Output Voltage Via FAULT/MSEL Pin

  - 2.5V for RDRAM Memory

  - 3.3V for SDRAM Memory

• Under-Voltage Monitoring of All Outputs with Centralized FAULT Reporting

• Adjustable Soft-Start Function Eliminates 5VSB Perturbations

• Pb-Free Available (RoHS Compliant)

Absolute Maximum Ratings

Supply Voltage, V_5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V

DLA, DRV2 . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V12V +0.3V

All Other Pins. . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3 [5kV]

Recommended Operating Conditions

Supply Voltage, V_5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Secondary Bias Voltage, V_12V. . . . . . . . . . . . . . . . . . . . +12V ±10%

Digital Inputs, V_S3, V_S5, V_EN3VDL, V_EN5VDL . . . . . . . . . .0 to +5.5V

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C

Thermal Information

Thermal Resistance (Typical, Note 1)                          θ_JA (°C/W)

      SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

     (SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. θ_JA is measured with the component mounted on an evaluation PC board in free air.

Block Diagram