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Propagation Delay NA, NB, NC, ND To NY: | 8 Ns | Input Capacitance: | 3.5 PF |
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Power Dissipation Capacitance Per Package: | 22 PF | Output Capability: | Standard |
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74HC20D Integrated Circuit Chip , Dual 4 input NAND gate IC Electronic Components
Dual 4-input NAND gate 74HC/HCT20
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT20 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT20 provide the 4-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL | PARAMETER | CONDITIONS | TYPICAL | UNIT | |
HC | HCT | ||||
tPHL/ tPLH | propagation delay nA, nB, nC, nD to nY | CL = 15 pF; VCC = 5 V | 8 | 13 | ns |
CI | input capacitance | 3.5 | 3.5 | pF | |
CPD | power dissipation capacitance per package | notes 1 and 2 | 22 | 17 | pF |
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
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