AT91 ARM Thumb-based Microcontrollers ARM-based Embedded MPU DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR AT91SAM9G45

AT91 ARM Thumb-based Microcontrollers

Features

• 400 MHz ARM926EJ-S™ ARM® Thumb® Processor

– 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU

• Memories – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

– External Bus Interface supporting 4-bank DDR2/LPDDR,

SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC

– One 64-KByte internal SRAM,

single-cycle access at system speed

or processor speed through TCM interface

– One 64-KByte internal ROM, embedding bootstrap routine

• Peripherals

– LCD Controller supporting STN and TFT displays up to 1280*860

– ITU-R BT. 601/656 Image Sensor Interface

– USB Device High Speed, USB Host High Speed

and USB Host Full Speed with OnChip Transceiver

– 10/100 Mbps Ethernet MAC Controller

– Two High Speed Memory Card Hosts (SDIO, SDCard, MMC)

– AC'97 controller – Two Master/Slave Serial Peripheral Interfaces

– Two Three-channel 32-bit Timer/Counters

– Two Synchronous Serial Controllers (I2S mode)

– Four-channel 16-bit PWM Controller

– Two Two-wire Interfaces

– Four USARTs with ISO7816, IrDA, Manchester and SPI modes

– 8-channel 10-bit ADC with 4-wire Touch Screen support

Description

The ARM926EJ-S based AT91SAM9G45 features the frequently demanded combination of user interface functionality and high data rate connectivity, including LCD Controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400MHz and multiple 100+ Mbps data rate peripherals, the AT91SAM9G45 has the performance and bandwidth to the network or local storage media to provide an adequate user experience.

The AT91SAM9G45 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and distributed memory including a 64- KByte SRAM which can be configured as a tightly coupled memory (TCM) sustains the high bandwidth required by the processor and the high speed peripherals.

The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing. The AT91SAM9G45 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes.

After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0 allowing the system to start on the internal RC oscillator. The programmer controls by software the slow clock switching and so must take precautions during the switching phase.