PIC18LF6722-I/PT IC Chip 64/80-Pin 1-Mbit Enhanced Flash Microcontrollers

 

PIC18F6627/6722/8627/8722

64/80-Pin 1-Mbit Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

 

Power-Managed Modes:

• Run: CPU on, peripherals on

• Idle: CPU off, peripherals on

• Sleep: CPU off, peripherals off

• Idle mode currents down to 15 µA typical

• Sleep current down to 0.2 µA typical

• Timer1 Oscillator: 1.8 µA, 32 kHz, 2V

• Watchdog Timer: 2.1 µA

• Two-Speed Oscillator Start-up

 

Flexible Oscillator Structure:

• Four Crystal modes, up to 25 MHz

• 4X Phase Lock Loop (PLL) (available for crystal and internal oscillators)

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal oscillator block:

  - 8 user selectable frequencies, from 31 kHz to 8 MHz

  - Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL

  - User tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor:

  - Allows for safe shutdown if peripheral clock stops

 

External Memory Interface (PIC18F8627/8722 only):

• Address capability of up to 2 Mbytes

• 8-bit or 16-bit interface

 

Peripheral Highlights:

• High current sink/source 25 mA/25 mA

• Four programmable external interrupts

• Four input change interrupts

• Two Capture/Compare/PWM (CCP) modules

 

Peripheral Highlights (Continued):

• Three Enhanced Capture/Compare/PWM (ECCP) modules:

  - One, two or four PWM outputs

  - Selectable polarity

  - Programmable dead-time

  - Auto-Shutdown and Auto-Restart

• Two Master Synchronous Serial Port (MSSP) modules supporting 2/3/4-wire SPI™

  (all 4 modes) and I2C™ Master and Slave modes

• Two Enhanced Addressable USART modules:

  - Supports RS-485, RS-232 and LIN 1.2

  - RS-232 operation using internal oscillator block (no external crystal required)

  - Auto-wake-up on Start bit

  - Auto-baud detect

• 10-bit, up to 16-channel Analog-to-Digital Converter module (A/D)

  - Auto-acquisition capability

  - Conversion available during Sleep

• Dual analog comparators with input multiplexing

 

Special Microcontroller Features:

• C compiler optimized architecture:

  - Optional extended instruction set designed to optimize re-entrant code

• 100,000 erase/write cycle Enhanced Flash program memory typical

• 1,000,000 erase/write cycle Data EEPROM memory typical

• Flash/Data EEPROM Retention: 100 years typical

• Self-programmable under software control

• Priority levels for interrupts

• 8 X 8 Single Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

  - Programmable period from 4 ms to 131s

• Single-supply In-Circuit Serial Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Wide operating voltage range: 2.0V to 5.5V

 

Pin Diagrams

 

64-Pin TQFP

Note 1: The CCP2/P2A pin placement is determined by the CCP2MX configuration bit and Processor mode settings.

 

80-Pin TQFP

Note 1: The CCP2/P2A pin placement is determined by the CCP2MX configuration bit and Processor mode settings.

          2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX configuration bit.

 

Absolute Maximum Ratings(†)

Ambient temperature under bias.........................................................................-40°C to +125°C

Storage temperature ......................................................................................... -65°C to +150°C

Voltage on any pin with respect to V_SS (except V_DD and MCLR) .............. -0.3V to (VDD + 0.3V)

Voltage on V_DD with respect to V_SS ..................................................................... -0.3V to +7.5V

Voltage on MCLR with respect to V_SS (Note 2) ..................................................... 0V to +13.25V

Total power dissipation (Note 1) ............................................................................................1.0W

Maximum current out of V_SS pin ........................................................................................300 mA

Maximum current into V_DD pin ...........................................................................................250 mA

Input clamp current, I_IK (V_I < 0 or V_I > V_DD)....................................................................... ±20 mA

Output clamp current, I_OK (V_O < 0 or V_O > V_DD) ............................................................. ±20 mA

Maximum output current sunk by any I/O pin.........................................................................25 mA

Maximum output current sourced by any I/O pin ...................................................................25 mA

Maximum current sunk by all ports ......................................................................................200 mA

Maximum current sourced by all ports .................................................................................200 mA

---

Note

1: Power dissipation is calculated as follows:

    Pdis = V_DD x {I_DD – ∑ I_OH} + ∑ {(V_DD – V_OH) x I_OH} + ∑(V_OL x I_OL)

2: Voltage spikes below VSS at the MCLR/VPP/RG5 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/V_PP/ RG5 pin, rather than pulling this pin directly to V_SS.

 

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

 

 

 

 

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